Search results for "Computer Hardware"
showing 10 items of 378 documents
Wireless ECG and cardiac monitoring systems: State of the art, available commercial devices and useful electronic components
2021
Abstract Wireless ElectroCardioGram (ECG) systems are employed in manifold application fields: tele-monitoring, sport applications, support to ageing people at home, fetal ECG, wearable devices and ambulatory monitoring. The presence of cables often hinders user’s free movements, alongside clinicians’ routine operations. Therefore, wireless ECG systems are desirable. This paper aims at reviewing the solutions described in the literature, besides commercially available devices and electronic components useful to setup laboratory prototypes. Several systems have been developed, different in terms of the adopted technology; when approaching the development of a wireless ECG system, some import…
High resolution Time of Flight determination based on reconfigurable logic devices for future PET/MR systems
2013
Abstract This contribution shows how to perform Time of Flight (TOF) measurements in PET systems using low-cost Field Programmable Gate Array (FPGA) devices with a resolution better of 100 ps. This is achieved with a proper management of the FPGA internal resources and with an extremely careful device calibration process including both temperature and voltage compensation. Preliminary results are reported.
High Performance FOC for Induction Motors with Low Cost ATSAM3X8E Microcontroller
2018
In this paper the Authors present the Arduino Due board application for an induction motor field oriented control (FOC) algorithm. The low cost Arduino Due board is equipped with a ATSAM3X8E microcontroller that performs the algorithm calculation, data processing, current signals and speed/position data acquisition. The control algorithm has been developed with the help of the open source Arduino integrated development environment, whereas a user friendly control interface, used to manage the speed or position set point, has been developed in Java language by means of an other open source software, namely, Processing. An experimental test bed has been set up in order to validate the FOC sys…
Nanoseconds Timing System Based on IEEE 1588 FPGA Implementation
2019
Clock synchronization procedures are mandatory in most physical experiments where event fragments are readout by spatially dislocated sensors and must be glued together to reconstruct key parameters (e.g. energy, interaction vertex etc.) of the process under investigation. These distributed data readout topologies rely on an accurate time information available at the frontend, where raw data are acquired and tagged with a precise timestamp prior to data buffering and central data collecting. This makes the network complexity and latency, between frontend and backend electronics, negligible within upper bounds imposed by the frontend data buffer capability. The proposed research work describ…
The ATLAS Level-1 Calorimeter Trigger: PreProcessor implementation and performance
2012
The PreProcessor system of the ATLAS Level-1 Calorimeter Trigger (L1Calo) receives about 7200 analogue signals from the electromagnetic and hadronic components of the calorimetric detector system. Lateral division results in cells which are pre-summed to so-called Trigger Towers of size 0.1 × 0.1 along azimuth (phi) and pseudorapidity (η). The received calorimeter signals represent deposits of transverse energy. The system consists of 124 individual PreProcessor modules that digitise the input signals for each LHC collision, and provide energy and timing information to the digital processors of the L1Calo system, which identify physics objects forming much of the basis for the full ATLAS fi…
Kefiran-based Scaffolds For Biomedical Applications
2018
Kefiran is an exopolysaccharide produced by microorganisms present in kefir grains, with several health promoting properties. A optimized protocol was developed for the separation of kefiran from kefir grains, allowing to reach a yield 4÷5 % without using toxic or expensive chemicals. The capability of kefiran to produce scaffold via Thermally Induced Phase Separation (TIPS) technique was investigated and porous scaffolds structure was obtained. Separated kefiran and scaffolds were analyzed via DSC and different thermal properties between purified kefiran and scaffold were revealed. XRD analysis revealed different structure between kefiran and scaffolds. The porous scaffold structure can be…
Installation and commissioning of the TileCal Read-Out Drivers
2007
TileCal is the hadronic tile calorimeter of the ATLAS experiment at LHC/CERN. The main component of the TileCal back-end electronics is the Read-Out Driver (ROD). The ROD system is placed between the first and the second level trigger and it is the responsible for processing the data gathered by the detector. The principal devices of the RODs are the Digital Signal Processors (DSPs) mounted in the Processing Units (PUs) daughterboards. The architecture and functionality of the RODs are briefly explained. Then, it is presented the ROD system installation in the ATLAS electronics cavern. Currently, the RODs are being used for the detector commissioning. It is detailed the Detector and Verific…
A Formal Model for Developing of the self-Diagosing and Self-Repairing 8-Bits Microprocessor, and Its Investigation Using Simulation
1986
Abstract The complete model of functional diagnostics is theoretically described. It specifies the conditions, which must be satisfied if the system to be self-diagnosable. The general principles of constructing self-diagnosable systems are enumerated. The model enables the realization of self-renewal, too. The model has been developed on the basis of the works by Preparata, Metze, Chien (1967) and Hakimi, Amin (1974) . The model contains a method of diagnostics completely separeted from the physical structure of the system. Recent results (Gruber, 1978; Swiatek, 1982) indicate that it is only necessary to know the set of transformations realized by the circuit. The model has been applied t…
Concept of virtual machine based high resolution display wall
2014
This paper presents the scalability and hardware dependency problems found in existing solutions in the high resolution display wall domain and proposes a new solution. Authors propose hosting the system that provides the visual content for the display wall inside a virtual machine. In such way any needed configuration of displays and resolutions can be applied to the graphics processing unit simulated by the virtualization system. The frame buffer content of the virtual graphics processing unit is then split, encoded with H.264 and sent over gigabit Ethernet as an RTP stream to the display wall. The display wall is driven by Raspberry Pi embedded devices that receive the stream, decode it …
Pre-production validation of the ATLAS level-1 calorimeter trigger system
2006
The Level-1 Calorimeter Trigger is a major part of the first stage of event selection for the ATLAS experiment at the LHC. It is a digital, pipelined system with several stages of processing, largely based on FPGAs, which perform programmable algorithms in parallel with a fixed latency to process about 300 Gbyte/s of input data. The real-time output consists of counts of different types of trigger objects and energy sums. Prototypes of all module types have been undergoing intensive testing before final production during 2005. Verification of their correct operation has been performed stand-alone and in the ATLAS test-beam at CERN. Results from these investigations will be presented, along …